8GB Dual-Rank PC2-5300 DDR2 667MHz CL5 (5-5-5) SDRAM FB-DIMM, ECC Fully Buffered

SKU: 1236190

Manufacturer: KINGSTON

MPN: KVR667D2D4F5/8G

Price: $285.48

Availability: Special Order

PRODUCT DESCRIPTION

ValueRAM’s 8GB (1024M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully buffered" ECC "dual rank" memory module. This module is based on eighteen stacked 1024M x 4-bit (thirty-six 512M x 4-bit) 667MHz DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer).

Overview:

ValueRAM’s 8GB (1024M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully buffered" ECC "dual rank" memory module. This module is based on eighteen stacked 1024M x 4-bit (thirty-six 512M x 4-bit) 667MHz DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer).

Specifications:

Description: 8GB 667MHz DDR2 ECC Fully Buffered CL5 DIMM Dual Rank, x4
Detailed Specifications: Standard 1024M X 72 ECC 667MHz 240-pin Fully Buffered DIMM (SDRAM-DDR2, 1.8V, CL5, FBGA, Gold)
Mfgr's System P/N's: N/A
Form Factor: Memory Module
Pieces/Unit: 1
Warranty: Lifetime


Fully Buffered DIMM Technology Overview

Fully Buffered DIMM (or FB-DIMM) is a memory solution which can be used to increase reliability, speed and density of memory systems. Traditionally, data lines from the memory controller have to be connected to data lines in every DRAM module. As memory width, as well as access speed, increases, the signal degrades at the interface of the bus and the device. This limits the speed and/or the memory density. FB-DIMMs take a different approach to solve this problem. As with nearly all RAM specifications, the FB-DIMM specification was published by JEDEC.

Fully Buffered DIMM architecture introduces an Advanced Memory Buffer (AMB) between the memory controller and the memory module. Unlike the parallel bus architecture of traditional DRAMs, a FB-DIMM has a serial interface between the memory controller and the AMB. This enables an increase to the width of the memory without increasing the pin count of the memory controller beyond a feasible level. With this architecture, the memory controller does not write to the memory module directly, rather it is done via the AMB. The AMB can thus compensate for signal deterioration by buffering and resending the signal. In addition, the AMB can also offer error correction, without posing any overhead on the processor or the memory controller. It can also use the Bit Lane Failover Correction feature to identify bad data paths and remove them from operation, which dramatically reduces command/address errors. Also, since reads and writes are buffered, they can be done in parallel by the memory controller. This allows simpler interconnects, more memory bandwidth, and (in theory) hardware-agnostic memory controller chips (such as DDR2 and DDR3) which can be used interchangeably. The downside to this approach is that it introduces latency to the memory request. However, the approach should allow higher memory speeds in the future thus obviating this concern.